`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:50:16 03/31/2014 
// Design Name: 
// Module Name:    clock_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_div(clk, vga_clk, refresh_clk
    );
	 input clk;
	 
	 output vga_clk, refresh_clk;
	 reg vga_clk = 1'b0;
	 reg refresh_clk =1'b0;
	 
	 
	 reg [19:0] counter = 2'b0;
	 
	 
	 always@(posedge clk)
	 counter <= counter + 1'b1;
	 
    always @(posedge clk)
	 if(counter[1] == 1'b1) vga_clk <= 1'b1;
	 else vga_clk <= 1'b0;
	 
	 always @(posedge clk)
	 if(counter[19] == 1'b1) refresh_clk <= 1'b1;
	 else refresh_clk <= 1'b0;

endmodule
